The present invention generally relates to the field of integrated circuits. More particularly, the present invention relates to systems and arrangements to interconnect cells and structures within cells formed in a substrate of an integrated circuit to enhance cell density and improve the across chip line variance (ACLV) tolerance for the integrated circuit.
Typical integrated circuit designs incorporate several metallization layers on top of a substrate to interconnect structures of cells formed in the substrate. In current designs, cells typically include complimentary metal oxide semiconductor (CMOS) circuits. CMOS circuits include p-type metal oxide semiconductor (PMOS) and n-type metal oxide semiconductor (NMOS) transistors formed from diffused areas of silicon and polycrystalline silicon, often referred to as polysilicon. The polysilicon areas are formed on top of a gate oxide above the diffused areas to form gates. The polysilicon areas also couple with the diffused areas on opposing sides of the gate to form electrodes for the source and drain of the transistors. Formation of the metallization layers over the substrate facilitates interconnection of the transistors to form more complex devices such as NAND gates, inverters, and the like.
The metallization layers utilize lines and vias to interconnect the transistors in each of the cells as well as to interconnect the cells to form the integrated circuit such as a processor, state machine, or memory. Lines typically reside in parallel paths within each layer. Lines in adjacent layers often run perpendicular to one another although lines in adjacent layers are separated by a non-conductive passivation layer also referred to as an inter-level dielectric layer such as, e.g., silicon oxide. The silicon oxide is etched to form the vias, which interconnect the lines of various metallization layers in accordance with the circuit design. Inputs and outputs of the integrated circuit are brought to a surface with vias to bond the circuits with pins of a chip package. The chip package typically includes an epoxy or ceramic that encloses the integrated circuit to protect the circuit from damage and pins to facilitate a connection between the inputs and outputs of the integrated circuit and, e.g., a printed circuit board.
As generations of integrated circuits are scaled down to increase functionality and speed available in a chip package, designers must continually scale down cell structures to smaller and smaller dimensions to increase the density of cells per area of the substrate. In fact, the scaling theory has predicted that processor sizes will decrease by half in each generation so a 50% area scalar is a goal when designing a new smaller technology generation of integrated circuits. Further, to take advantage of the smaller cells, the lines must be formed at smaller pitches.
In recent technology generations, numerous design constraints and rules have been developed that bound the patterns of cells in an integrated circuit. The rules and constraints take into consideration margins of error in locating the cells in the substrate, ways to reduce the magnitude of leakage, as well as many other considerations to assure the performance of the resulting integrated circuit. Rules delineate minimum distances between structures of cells, lines, vias, and the like. Metal direction relative to the gate material, metal layer chosen for power distribution within the cell, cell height, metal pitch, etc., are all constraints of a chosen pattern or physical layout of the cells. For example, one critical constraint is related to the width of the polysilicon gate material. The width of polysilicon gate material defines the length of the channel of a device. Longer channels add more delay to the response of a device, which is sometimes desirable. Many current designs, however, interconnect two or more short channel devices in series to create long channel devices thus reducing hardships involved with building long channel devices into the integrated circuits.
Another critical constraint is the metal pitch. Metal pitch determines the accessibility of cells so metal pitch directly impacts the cell density of the integrated circuit. Further, the length of interconnections between cells impacts the performance. For instance, longer lines have increased resistance, increasing heat dissipation in the integrated circuit. Longer lines also increase the capacitance of the overall design. Thus, while the first metallization layer is typically set to the tightest wire pitch, all remaining metallization layers of common thickness are constrained to a constant minimum metal pitch that facilitates interconnection of the cells. Current integrated circuits typically have six to eight metallization layers.
To meet such design rules and constraints and to maximize cell density, one semi-custom design technique involves creating a standard library of cells. The cell heights and widths are constrained to integrals of a standard grid so cells may be placed next to each other horizontally and vertically within the grid without violating the rules and constraints for the integrated circuit. The standard grid is an integral of the wiring pitch. Further, the cells are constrained to a constant cell height but the width of each cell may vary to accommodate various cell configurations while maximizing cell density for any combination of cells utilized to build the integrated circuit.
In most cases, the technology minimum ground rules are generally used to define each cell's physical architecture and minimizing the cell width for a particular cell improves the cell density for the integrated circuit. In the past, the polysilicon, or device gate material, was not required to be on a standard or single pitch (width plus space) so the width of the cells could be minimized by placing the polysilicon anywhere such that the minimum polysilicon width plus space was not violated. The minimum space in this context, is the space required to contact a diffusion area with a via/contact between the polysilicon areas.
As technology features grow ever smaller, the ability to process like drawn objects of the same width within a tight tolerance across the chip has become very difficult. This across chip line variance (ACLV) effectively determines the fastest and leakiest devices as well as the slowest devices. Because the designer must address both worst-case and best-case extremes in performance and must also take into account the ever-increasing leakage current associated with very short channel devices, ACLV is receiving increased focus. One way to improve ACLV is to force all polysilicon to be the same width (device or channel length) and for it to be positioned at a common, fixed pitch.
While forcing the polysilicon to be at a fixed pitch improves the ACLV, the cell density is degraded. For instance, when considering development of a standard cell library, one such consideration is the cell wiring pitch. The cell height and width are generally defined as an integer multiple of the wiring pitch so every cell can be accessed via the wiring in the metallization layers. For purposes of the following illustrations, consider metallization layer one, M1, running horizontally and metallization layer two, M2, running vertically (orthogonal to M1). In this manner, all lines on odd numbered metallization layers run horizontally and all lines on even numbered metallization layers run vertically. This orthogonal arrangement, which is generally practiced, allows effective wiring. Accordingly, the width of the cell (horizontal) is generally defined as an integer number of M2 wiring tracks or pitches to allow any circuit to be placed next to any other circuit along the x-axis. Similarly, the height of the cell is an integer number of M1 tracks allowing any circuit to be placed next to any other circuit along the y-axis.
As a first illustration, consider the 90 nanometer (nm) technology and assume the polysilicon is running orthogonal to M1 and in parallel to M2, the M1 pitch is relaxed to match the larger M2 pitch, and the M2 pitch is set to 0.28 micrometer (um). In one 90 nm technology, for instance, the polysilicon gate pitch can be as short as 0.22 um with no requirement for the polysilicon to be positioned at a common, fixed pitch. Thus, the polysilicon gate pitch is smaller than the M2 pitch to allow gates to be placed wherever they produce the best cell density. Note, that the cell width must be a multiple of the 0.28 um M2 pitch to allow any circuit to be placed next to any other circuit on the x-axis as stated above. Hence, any inefficiency in the cell's layout can result in an increase in cell width from n-tracks to n+1 tracks. Stated another way, if the cell layout misses terminating on the M2 wiring track grid by even one layout grid snap, which is typically 0.01 um, then the cell width must be increased to the next minimum step off, or offset, of 0.28 um. This can invoke serious deficiencies in density.
The new design constraint for the 65 nm technology generation of integrated circuits that forces the polysilicon to be placed at a common pitch, removes the ability to adjust the position of the polysilicon to minimize the width of a cell. Thus, to accommodate the standard cell design, the minimum grid with respect to cell width is the least common multiple of the wiring pitch and the polysilicon gate pitch.
In the 65 nm technology, the wiring pitch in the metallization layers is reduced to, e.g., 0.20 um to maximize cell density with respect to the ability to interconnect the smaller cells. Assume also, for example, that the polysilicon pitch is fixed at 0.25 um. Thus, the least common multiple of the metal pitch and the polysilicon pitch is 1.0 um or one micron. In other words, the minimum cell width for this design is five wiring tracks. If the cell design misses 1.0 um by 0.01 um (i.e., the cell width is 1.01 um), the next minimum step off is 2.0 um so the cell is ten wiring tracks wide instead of five wiring tracks wide. As a result, a cell that utilizes six wiring tracks in the 90 nm technology may utilize ten wiring tracks in the 65 nm technology due to the common pitch requirement for the polysilicon, which is a 66% increase in the number of tracks consumed by the cell. Further, many cells in a standard cell library for the 65 nm technology can be designed with a cell width that is smaller than five wiring tracks.
What is needed is a layout strategy for a standard cell design that is consistent with this constant polysilicon pitch requirement to improve ACLV while minimizing the impact of the constant polysilicon pitch on cell density.